Network on Chip round table

European Space Agency, ESTEC

Noordwijk / The Netherlands

17th and 18th of September 2009


Proceedings & Synthesis note






Session 1: Introduction

Welcome address

Philippe Armbruster, Head of Data System Division (ESA / The Netherlands)


Why NoC for Space?

Philippe Perdu (CNES / France)


ESA IPs & SoCs developments

Laurent Hili (ESA / The Netherlands)


NoC tutorial

Ran Ginosar (Technion Institute of Technologies / Israel)




Session 2: Architectures part 1

NoC through real-life applications: LETI's experience

Fabien Clermidy (CEA – LETI / France) Cancelled


Asynchronous 3D NoCs

Hamed Sheibanyrad, Frederic Petrot (TIMA Laboratory / France)


Supporting Distributed Shared Memory on Multi-core NoCs with a Dual Micro coded Controller

Axel Jantsch (KTH / Sweden)


Generation of RTL-code and test facilities for on-chip TDM network

Geir Åge Noven (Kongsberg / Norway)




Session 3: Architectures part 2

Using network-on-chip technology for creating scalable programmable many-core system-on-chip architectures

Gerard Rauwerda (Recore Systems / The Netherlands)


NoC concepts with XPP-III

Eberhard Schuler (PACT / Germany)


Spidergon STNoC, the Interconnect Processing Unit (IPU)

Riccardo Locatelli (ST microelectronics / France)


The Real-Time Network on Chip Aethereal (including comparison with SpaceWire)

Kees Goossens (SOC Architectures and Infrastructure NXP Semiconductors / The Netherlands)


SoCWire: a SpaceWire inspired fault tolerant Network on Chip approach for reconfigurable System on Chip in Space applications

Bjorn Osterloh (Braunschweig Institute of Computer and Communication Network Engineering / Germany)


HOST (Hardware Operating System Technology)

Steve Parkes (University of Dundee / UK)




Session 4: Tools and design methodologies

Link between NoC Technology and programming model in a reconfigurable System on Chip

Domique Houzet (Institut National Polytechnique Grenoble / France)


A Theorem-Proving Based Approach for the Formal Verification of NoCs

Laurence Pierre (TIMA Laboratory / France)


OCCN and Virtual Platform for power estimation and fault tolerant routing

Constantin Papadas (ISD / Greece)




Session 5: Fault tolerant NoCs

Multi-level fault tolerance in 2D and 3D NoCs

Claudia Rusu (TIMA Laboratory / France)


Concepts for Robust NoC Communication

Martin Radetzki (Stuttgart University / Germany)




Session 6: Space applications

Network on a Chip – What might it mean for On-board Data Handling Systems?

Lester Waugh (Astrium / UK) Cancelled


From SoC to NoC based on SCOC3 HW & SW developments

Marc Souyri, Jean-François Coldefy, Franck Koebel, Vincent Lefftz (Astrium / France)




Session 7: Conclusion

Round table synthesis note

Laurent Hili (ESA / The Netherlands)